Friday, July 09, 2010

Actel Smartfusion

Yesterday, I went to Seattle for a presentation (they call it a "design workshop") on Atmel's Smartfusion devices.  They have combined their Flash-based FPGA with an ARM Cortex-M3, the usual micro-controller peripherals, and some configurable analog blocks to make a very flexible, mixed-signal, embedded device.  I brought home an eval board and some thoughts on their technology.



First, some background info.

I like Actel's FPGAs.  Their on-die Flash and anti-fuse FPGAs tend to be faster than Xilinx or Altera.  Actel seems to always put plenty of routing resources on the chip, unlike Xilinx which seems to always starve the routing.  Sure, Xilinx can route through logic cells, but then you end up with the occasional 100nS signal delay.  Altera seems to fall in between Xilinx and Actel in routability (and thus real world speed - ignore the raw gate delays).

What's in a SmartFusion device?  Basically, its a nice ARM Cortex-M3 based 100MHz, 32-bit MCU with all the peripherals and memory you would expect, some configurable analog functions, plus an Actel Flash FPGA fabric.  Here is the datasheet.  A quick rundown:
  • SPI, I2C, UART, 32-bit timers, watchdog, RTC, on-ship oscillators (classic MCU stuff)
  • 8-channel DMA, Priority interrupt controller, external memory controller, Ethernet MAC (nice Cortex-M3 support)
  • Embedded SRAM (dual port!), FLASH, and a bit of EEPROM
  • 12-bit A/D and D/A, comparators
  • Flash programmed FPGA with 4Kbit SRAM blocks
  • All tied together by an AHB and APB busses
  • JTAG programming and debugging

The CPU and perhipherals are implemented in gates aka "hard macros", not FPGA soft macros.  This avoids  issues with typical FPGA implementations of embedded controllers.  Soft macro CPUs take up too many FPGA resources and under-perform in speed.  So you can end up with a $50 FPGA-based part that performs like a $5 Atmel or PIC device.

My take aways from the class (more or less from the bad to the good):

No USB interface.  IMO, that's as important as Ethernet for a 32-bit MCU embedded design.  They need to add that in the next generation.

FPGA tools have slowly improved over the years.  Early on, FPGA tools were a collection of totally separate programs with completely different UI's for each stage: design capture, simulation, timing analysis, synthesis, routing.  Over time, the different FPGA vendors have added nice front ends that tie those bits together and run most of them in the background.  Unfortunately, with the CPU, hard peripherals, and analog functions being added to the FPGA, we're back to a very modal design model where you are obviously launching different tools from different vendors to get things done.  By the end of the class, by brain was spinning.  You need a very large poster to diagram the roadmap you must navigate to produce a design.  At this point, it is not for the feint of heart.  Certainly not for the hobbiest.

Too costly.  The mid-sized part with 200K FPGA gates is about $50.  I don't know the cost of the 600K device, but it must be well above $200.  I can get a 32-bit ARM MCU and a nice sized FPGA for under $50.  The 60K device, to be released latter this year, may be at a more interesting price point.

The programmable analog looked interesting.  Compared to a typical MCU with an A/D and maybe some comparators, the analog modules are more flexible and varied.  They include an "analog compute engine", which is really just a configurable state machine.  But it gives the designer more than the usual flexibility in configuring how the analog works, and offloads the CPU a bit for simple sequencing of the analog functions.  There is also a "post processing engine" that can do low-pass filtering and other transformations that really are better done in hardware than the general purpose CPU.

While I already complained about the tools, I really liked the MSS (microcontroller subsystem) configurator.  Atmel and Microchip need to study this and emulate this capability it for their MCU's, immediately. If Arduino added this functionality to their tools, it would really make the platform easier to use for people without a background in embedded design.

The tool presents you with a "block diagram" GUI view of the ARM CPU and hard macro peripherals.  Click on any function block to configure or disable it.  For example, set the SPI interface to master, disable an unused UART, set up a timer on an interrupt, etc.

Then the magical happens.  The tool will generate a software shell with all of the drivers for the peripherals, initial setup functions, and all the .c and .h files set up and ready for you to add your code into the main() function.  No more hunting around the web and downloading what you hope is the right SPI code that will work with your part.  A lot less adding include files to fulfill dependencies in the drivers.  Its like Arduino on mega-doses of steroids.  That UART block you disabled - it will be set up for zero power.  The SPI interface - just look at the function prototypes and you know how to read() and write() to your SPI peripherals.

If you are uncertain about how to use any of the MSS devices, you can have the tool generate a little example code that will run on the evaluation board,  You can then see and experiment with working code.

The MSS tool also supports very easily adding any of the common embedded peripherals to the FPGA and it will hook them up to the ARM through the ABH bus, set up the memory map, and supply the drivers and the setup code.  All with drag-n-drop.  You can add 5 UARTS with no Verilog (or VHDL, your choice) coding required.  But the Verilog is there and editable.  If you need a 64-byte FIFO on your UART, you can get into the code and add it.

I know Freescale has something similar in their Processor Expert tool, and probably others as well.  Maybe there is a costly 3rd party tool out there that does this.  But I haven't had an opportunity to use those yet.  Atmel really needs something like this, with the variability in how their different devices implement the same peripheral functions.  Microchip is a bit more consistent with their peripherals, but this would still be a nice feature for their flow.

Arduino, thanks to being on a small subset of parts, would have the easiest time implementing this, and their user base needs it the most.  I think it could help expand Arduino from 100,000 users to 10 million.

The eval board

The SmrtFusion eval board sold out immediately when Actel announced it.  They've had more batches built and they are now available. 

For $99 (or $50 for the board plus a day of training, which is what I did), you get their $50 A2F200KM3F SmartFusion part on a board with a (tiny) I2C OLED display, some buttons and LEDs, a 10/100 Ethernet port, external SPI Flash memory, an expansion header, and a USB interface.

The USB interface is implemented in a separate part, not the A2F200K.  It is used for programming and debug.  It can also be used to send data from an application running on the FPGA through a UART port to the PC using serial over USB.

Basically, you have a way to play with all of the different I/O features on the chip.  This comes in handy with the MSS tool's ability to generate example code.

There are several jumper switches on the board.  The silk screen is so small, it almost takes a magnifying glass to make out which is which.  One jumper has to be constantly changed as you go between programing the part and debugging.  That's a pain.  At the least, they should have a slide switch, and preferably figure out a way to eliminate that jumper.

3 comments:

Christian said...

Nice blog. Thanks for taking the time to relate your first-hand experience with our SmartFusion. If I may, I'd like to add a few comments.

Pricing: The $50 price point for an A2F200 is for unitary volume. High volume pricing is often much lower and is meant to compete with the pricing of a combined 32bit MCU and an equivalent FPGA. For the A2F500, it is not going to be 2.5x what the A2F200 is, unlike what the part number could lead you to believe. The FPGA section of the device is indeed 2.5x the size, but the MSS and Analog Front-End don't grow in a similar fashion. Thus, if you look at some of our distributors, it's more like 1.5x the price of an A2F200.

Your comment about USB is well taken. We've heard it many times since we started engaging with customers. We're keeping this in mind for our next-gen devices.

I've also made sure that our Silicon and Software Engineering teams read your comments about the device and software. It's very insightful and will help us improve the product and its ecosystem.

One last detail. Many people often confuse Actel with Atmel (our bigger cousin). I think that's happened in one place in this blurb.

Thanks again for drafting this up!

SiliconFarmer said...

Christian, thanks for the comments.

It is good to hear that the larger device's cost doesn't go up linearly with the FPGA gates.

I'm still looking forward to hearing the cost of the smaller device. In the past, I've used large FPGA's for prototyping ASICs, but I've gone to production with designs containing an MCU and a small FPGA.

I've fixed the Actel/Atmel mixup in the text. Sorry about that!

Robert said...

One of the best summaries I've seen on the part, including some really rare price information. Thank you!
Did you ever check out the PSoC5? It has less FPGA, rather PLD capabilities, IMHO better analog IP and the major tool PSoC Creator supports GNU, so it can all be free. For all I know, pricing is somewhat lower but it is also hard to find. I only heard about pricing through the grapevine.
It's going to be interesting how these two will be growing in the programmable SOC market
Bob